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| M-8880 DTMF Transceiver * * * * * * * * * * * * * Advanced CMOS technology for low power consumption and increased noise immunity Complete DTMF transmitter/receiver in a single chip Standard 6500/6800 series microprocessor port Central office quality and performance Adjustable guard time Automatic tone burst mode Call progress mode Single +5 Volt power supply 20-pin DIP and SOIC packages 2 MHz microprocessor port operation Inexpensive 3.58 MHz crystal No continuous f2 clock required, only strobe Applications include: paging systems, repeater systems/mobile radio, interconnect dialers, PBX systems, computer systems, fax machines, pay telephones, credit card verification Figure 1 Pin Diagram Functional Description M-8880 functions consist of a high-performance DTMF receiver with an internal gain setting amplifier and a DTMF generator that contains a tone burst counter for generating precise tone bursts and pauses. The call progress mode, when selected, allows the detection of call progress tones. A standard 6500/6800 series microprocessor interface allows access to an internal status register, two control registers, and two data registers. Input Configuration The input arrangement consists of a differential input operational amplifier and bias sources (VREF) for biasing the amplifier inputs at VDD/2. Provisions are made for the connection of a feedback resistor to the op-amp output (GS) for gain adjust- The M-8880 is a complete DTMF Transmitter/Receiver that features adjustable guard time, automatic tone burst mode, call progress mode, and a fully compatible 6500/6800 microprocessor interface. The receiver portion is based on the industry standard M-8870 DTMF Receiver, while the transmitter uses a switched-capacitor digital-to-analog converter for low-distortion, highly accurate DTMF signaling. Tone bursts can be transmitted with precise timing by making use of the automatic tone burst mode. To analyze call progress tones, a call progress filter can be selected by an external microprocessor. Figure 2 Block Diagram 40-406-00012, Rev. G www.clare.com Page 1 M-8880 Figure 3 Single-Ended Input Configuration Figure 4 Differential Input Configuration ment. In a single-ended configuration, the input pins should be connected as shown in Figure 3. Figure 4 shows the necessary connections for a differential input configuration. Receiver Section The low and high group tones are separated by applying the DTMF signal to the inputs of two sixth-order switched capacitor bandpass filters with bandwidths that correspond to the low and high group frequencies listed in Table 2. The low group filter incorporates notches at 350 and 440 Hz, providing excellent dial tone rejection. Each filter output is followed by a single-order switched capacitor filter that smooths the signals prior to limiting. Limiting is performed by high-gain comparators with hysteresis to prevent detection of unwanted low-level signals. The comparator outputs provide full-rail logic swings at the incoming DTMF signal frequencies. A decoder employs digital counting techniques to determine the frequencies of the incoming tones, and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals (such as voice), while tolerating small deviations in frequency. The algorithm provides an optimum combination of immunity to talkoff with tolerance to interfering frequencies (third tones) and noise. When the detector recognizes the presence of two valid tones (referred to as "signal condition"), the early steering (ESt) output goes to an active state. Any subsequent loss of signal condition will cause ESt to assume an inactive state. Steering Circuit: Before a decoded tone pair is registered, the receiver checks for a valid signal duration (referred to as "character recognition condition"). This check is performed by an external RC time constant driven by ESt. A logic high on ESt Table 1 Pin Functions Name IN+ INGS VREF VSS OSC1 OSC2 TONE R/W CS RS0 2 IRQ/CP Description Noninverting op-amp input. Inverting op-amp input. Gain select. Gives access to output of front end differential amplifier for connection of feedback resistor. Reference voltage output. Nominally VDD/2 is used to bias inputs at mid-rail. Negative power supply input. DTMF clock/oscillator input. Clock output. A 3.5795 MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit. Dual tone multifrequency (DTMF) output. Read/write input. Controls the direction of data transfer to and from the microprocessor and the receiver/transmitter. TTL compatible. Chip select. TTL input (CS = 0 to select the chip). Register select input. See Table 6. TTL compatible. System clock input. May be continuous or strobed only during read or write. TTL compatible. Interrupt request to microprocessor (open-drain output). Also, when call progress (CP) mode has been selected and interrupt enabled, the IRQ/CP pin will output a rectangular wave signal representative of the input signal applied at the input op-amp. The input signal must be within the bandwidth limits of the call progress filter. See Figure 11 Microprocessor data bus. TTL compatible. Early steering output. Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. Steering input/guard time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant; its state is a funciton of ESt and the voltage on St. Positive power supply input. D0 - D3 ESt St/GT VDD 40-406-00012, Rev. G www.clare.com Page 2 M-8880 causes VC (see Figure 5) to rise as the capacitor discharges. Provided that the signal condition is maintained (ESt remains high) for the validation period (tGTP), VC reaches the threshold (VTSt) of the steering logic to register the tone pair, latching its corresponding 4-bit code (see Table 2) into the receive data register. Table 2 Tone Encoding/Decoding FLOW 697 697 697 770 770 770 852 852 852 941 941 FHIGH 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 Digit 1 2 3 4 5 6 7 8 9 0 D3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 D2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 D1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (dropout) too short to be considered a valid pause. This capability, together with the ability to select the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements. Guard Time Adjustment: The simple steering circuit shown in Figure 5 is adequate for most applications. Component values are chosen according to the formula: tREC = tDP + tGTP TID = tDA + tGTA The value of tDP is a device parameter and tREC is the minimum signal duration to be recognized by the receiver. A value for C1 of 0.1 F is recommended for most applications, leaving R1 to be selected by the designer. Different steering arrangements may be used to select independently the guard times for tone present (tGTP) and tone absent (tGTA). This may be necessary to meet system specifications that place both accept and reject limits on both tone duration and interdigit pause. Guard time adjustment also allows the designer to tailor system parameters such as talkoff and noise immunity. Increasing tREC improves talkoff performance since it reduces the probability that tones simulated by speech will maintain signal condition long enough to be registered. Alternatively, a relatively short tREC with a long tDO would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone dropouts are required. Design information for guard time adjustment is shown in Figure 6. * 941 1477 # 697 1633 A 770 1633 B 852 1633 C 941 1633 D 0 = logic low, 1 = logic high At this point the StGT output is activated and drives VC to VDD. StGT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the output latch to settle, the delayed steering output flag goes high, signaling that a received tone pair has been registered. It is possible to monitor the status of the delayed steering flag by checking the appropriate bit in the status register. If interrupt mode has been selected, the IRQ/CP pin will pull low when the delayed steering flag is active. Figure 6 Guard Time Adjustment Figure 5 Basic Steering Circuit Call Progress Filter A call progress (CP) mode can be selected, allowing the detection of various tones that identify the progress of a telephone call on the network. The call progress tone input and DTMF input are common; however, call progress tones can only be detected when the CP mode has been selected. DTMF signals cannot be The contents of the output latch are updated on an active delayed steering transition. This data is presented to the 4-bit bidirectional data bus when the receive data register is read. 40-406-00012, Rev. G www.clare.com Page 3 M-8880 detected if the CP mode has been selected (see Table 3). Figure 7 indicates the useful detect bandwidth of the call progress filter. Frequencies presented to the input (IN+ and IN-) that are within the "accept" bandwidth limits of the filter are hard-limited by a high-gain comparator with the IRQ /CP pin serving as the output. The square wave output obtained from the schmitt trigger can be analyzed by a microprocessor or counter arrangement to determine the nature of the call progress tone being detected. Frequencies in the "reject" area will not be detected, and consequently there will be no activity on IRQ /CP as a result of these frequencies. accuracy. When there is no tone output signal, the TONE pin assumes a DC level of 2.5 volts (typically). A bandwidth limiting filter is incorporated to attenuate distortion products above 4 KHz. Burst Mode: Certain telephony applications require that generated DTMF signals be of a specific duration, determined either by the application or by any of the existing exchange transmitter specifications. Standard DTMF signal timing can be accomplished by making use of the burst mode. The transmitter is capable of issuing symmetric bursts/pauses of predetermined duration. This burst/pause duration is 51 ms 1 ms, a standard interval for autodialer and central office applications. After the burst/pause has been issued, the appropriate bit is set in the status register, indicating that the transmitter is ready for more data. The timing described is available when the DTMF mode has been selected. However, when call progress (CP) mode is selected, a secondary burst/pause time is available that extends this interval to 102 ms 2 ms. The extended interval is useful when precise tone bursts of longer than 51 ms duration and 51 ms pause are desired. Note that when CP mode and burst mode have been selected, DTMF tones may be transmitted only and not received. In applications requiring a nonstandard burst/pause time, use a software timing loop or external timer. This provides the timing pulses when the burst mode is disabled by enabling and disabling the transmitter. Figure 7 Call Progress Response DTMF Generator The DTMF transmitter used in the M-8880 is capable of generating all 16 standard DTMF tone pairs with low distortion and high accuracy. All frequencies are derived from an external 3.58 MHz crystal. The sinusoidal waveforms for the individual tones are digitally synthesized using row and column programmable dividers and switched capacitor digital-to-analog converters. The row and column tones are mixed and filtered, providing a DTMF signal with low total harmonic distortion and high accuracy. To specify a DTMF signal, data conforming to the encoding format shown in Table 2 must be written to the transmit data register. Note that this is the same as the receiver output code. The individual tones that are generated (fLOW and fHIGH) are referred to as low-group and high-group tones. Typically, the high-group to low-group amplitude ratio (twist) is 2 dB to compensate for high-group attenuation on long loops. Operation: During write operations to the transmit data register, 4-bit data on the bus is latched and converted to a 2 of 8 code for use by the programmable divider circuitry to specify a time segment length that will ultimately determine the tone frequency. The number of time segments is fixed at 32, but the frequency is varied by varying the segment length. When the divider reaches the appropriate count as determined by the input code, a reset pulse is issued and the counter starts again. The divider output clocks another counter that addresses the sinewave lookup ROM. The lookup table contains codes used by the switched capacitor D/A converter to obtain discrete and highly accurate DC voltage levels. Two identical circuits are used to produce row and column tones, which are then mixed using a low-noise summing amplifier. The oscillator described needs no "startup" time as in other DTMF generators, since the crystal oscillator is running continuously, thus providing a high degree of tone burst The M-8880 is initialized on powerup sequence with DTMF mode and burst mode selected. Single-Tone Generation: A single-tone mode is available whereby individual tones from the low group or high group can be generated. This mode can be used for DTMF test equipment applications, acknowledgment tone generation, and distortion measurements. Refer to Table 4 for details. Distortion Calculations: The M-8880 is capable of producing precise tone bursts with minimal error in frequency (see Table 3). The internal summing amplifier is followed by a first-order low-pass switched capacitor filter to minimize harmonic components and intermodulation products. The total harmonic distortion for a single tone can be calculated using Equation 1, (see Figure 9) which is the ratio of the total power of all the extraneous frequencies to the power of the fundamental frequency expressed as a percentage. The Fourier components of the tone output correspond to V2f... Vnf as measured on the output waveform. The total harmonic distortion for a dual tone can be calculated using Equation 2 (see Figure 9). Table 3 Actual Frequencies vs. Standard Requirements Active Cell L1 L2 L3 L4 H1 H2 H3 H4 Output Frequency (Hz) Specified Actual 697 770 852 941 1209 1336 1447 1633 699.1 766.2 847.4 948.0 1215.9 1331.7 1471.9 1645.0 % Error + 0.30 - 0.49 - 0.54 + 0.74 + 0.57 - 0.32 - 0.35 + 0.73 40-406-00012, Rev. G www.clare.com Page 4 M-8880 Table 4 Control Register A Description Bit b0 b1 Name TOUT CP/DTMF Function Tone output Description b2 IRQ b3 RSET A logic 1 enables the tone output. This function can be implemented in either the burst mode or nonburst mode. Mode control In DTMF mode (logic 0), the device is capable of generating and receiving DTMF signals. When the call progress (CP) mode is selected (logic 1), a 6th-order bandpass filter is enabled to allow call progress tones to be detected. Call progress tones within the specified bandwidth will be presented at the IRQ/CP pin in rectangular wave format if the IRQ bit has been enabled (b2 =1). Also, when the CP mode and burst mode have both been selected, the transmitter will issue DTMF signals with a burst and pause of 102 ms (typ) duration. This signal duration is twice that obtained from the DTMF transmitter, if DTMF mode had been selected. Note that DTMF signals cannot be decoded when the CP mode has been selected. Interrupt enable A logic 1 enables the interrupt mode. When this mode is active and the DTMF mode has been selected (b1 = 0), the IRQ/CP pin will pull to a logic 0 condition when either (1) a valid DTMF signal has been received and has been present for the guard time or (2) the transmitter is ready for more data (burst mode only). Register select A logic 1 selects control register B on the next write cycle to the control register address. Subsequent write cycles to the control register are directed back to control register A. Table 5 Control Register B Description Bit b0 Name BURST Function Burst mode Description b1 TEST b2 S/D b3 C/R A logic 0 enables the burst mode. When this mode is selected, data corresponding to the desired DTMF tone pair can be written to the transmit data register, resulting in a tone burst of a specific duration (see Table 12). Subsequently, a pause of the same duration is induced. Immediately following the pause, the status register is updated indicating that the transmit data register is ready for further instructions, and an interrupt will be generated if the interrupt mode has been enabled. Additionally, if call progress (CP) mode has been enabled, the burst and pause duration is increed by a factor of two. When the burst mode is not selected (logic 1), tone bursts of any desired duration may be generated. Test mode By enabling the test mode (logic 1), the IRQ/CP pin will present the delayed steering (inverted) signal from the DTMF receiver. Refer to Figure 11 (b3 waveform) for details concerning the output waveform. DTMF mode must be selected (CRA b1 = 0) before test mode can be implemented. Single/dual tone A logic 0 will allow DTMF signals to be produced. If single-tone generation is enabled (logic 1), eigeneration ther now or column tones (low or high group) can be generated depending on the state of b3 in control register B. Column/row When used in conjunction with b2 (above), the transmitter can be made to generate single-row or tones single-column frequencies. A logic0 will select row frequencies and a logic 1 will select column frequencies. VL and VH correspond to the low-group and high-group amplitude, respectively, and V2IMD is the sum of all the intermodulation components. The internal switched capacitor filter following the D/A converter keeps distortion products down to a very low level. DTMF Clock Circuit The internal clock circuit is completed with the addition of a standard 3.579545 MHz television color burst crystal. A number of M-8880 devices can be connected as shown in Figure 8 using only one crystal. Microprocessor Interface The M-8880 uses a microprocessor interface that allows precise control of transmitter and receiver functions. Five internal registers are associated with the microprocessor interface, which can be subdivided into three categories: data transfer, transceiver control, and transceiver status. Two registers are associated with data transfer operations. The receive data, read-only, contains the output code of the last valid DTMF tone pair to be decoded. The data entered in the transmit data register determines which tone pair is to be generated (see Table 2). Figure 8 Common Crystal Connection Data can only be written to the transmit data register. Transceiver control is accomplished with two control registers (CRA and CRB), occupying the same address space. A write operation to CRB can be executed by setting the appropriate bit in CRA. The following write operation to the same address will then be directed to CRB, and subsequent write cycles will then be redirected to CRA. Internal reset circuitry clears the control 40-406-00012, Rev. G www.clare.com Page 5 M-8880 registers on powerup; however, as a precautionary measure the initialization software should include a routine to clear the registers. Refer to Tables 3 and 4 for details on the control registers. The IRQ/CP pin can be programmed to provide an interrupt request signal on validation of DTMF signals, or when the transmitter is ready for more data (burst mode only). The IRQ/CP pin is configured as an open-drain output device and as such requires a pullup resistor (see Figure 10). Ordering Information M-888001P 20-pin plastic DIP M-8880-01SM 20-pin plastic SOIC M-8880-01T 20-pin plastic SOIC,Tape and Reel Figure 9 Equations Table 7 CRA Bit Postions Table 6 Internal Register Functions RS0 0 0 1 1 R/W 0 1 0 1 Function Write to transmitter Read from receiver Write to control register Read from status register b3 C/R b3 RSEL b2 IRQ b1 CP/DTMF b0 TOUT Table 8 CRB Bit Positions b2 S/D b1 TEST b0 BURST Figure 10 Application Circuit (Single-Ended Input) 40-406-00012, Rev. G www.clare.com Page 6 M-8880 Table 9 Status Register Description BIT b0 b1 b2 b3 IRQ Name Status Flag Set Status Flag Cleared Interrupt is inactive. Cleared after status register is read. Cleared after status register is read or when not in burst mode. Cleared after status register is read. Cleared on detection of a valid DTMF signal. Interrupt has occurred. Bi tone (b1) and/or bit 2 (b2) is set. Transmit data register Pause duration has terminated and transmitter is empty (burst mode only) ready for new data. Receive data register Valid data is in the receive data register. full Set on valid detection of the absence of a DTMF sigDelayed steering nal. Table 10 Absolute Maximum Ratings Parameter Symbol Value + 6.0 V max VDD Power supply voltage (VDD - VSS) Vdc VSS -0.3 V to VDD + 0.3 V Voltage on any pin 10 mA max IDD Current on any pin TA -40C to +85C Operating temperature TS -65C to +150C Storage temperature Note: Exceeding these ratings may cause permanent damage. Functional operation under these conditions is not implied. Table 11 DC Characteristics Parameter Operating supply voltage Operating supply current Power consumption Inputs High-level input voltage, OSC1 Low-level input voltage, OSC1 Input impedance (@ 1 kHz), IN+, INSteering threshold voltage Outputs High-level output voltage (no load), OSC2 Low-level output voltage (no load), OSC2 Output leakage current (VOH = 2.4V), IRQ VREF output voltage (no load) VREF output resistance Data Bus Low-level input voltage High-level input voltage Low-level output voltage (IOL = 1.6 mA) High-level output voltage (IOH = 400 A) Input leakage current (VIN = 0.4 to 2.4 V) Symbol VDD IDD PO VIHO VILO RIN VTSt VOHO VOLO IOZ VREF ROR VIL VIH VOL VOH IIZ Min 4.75 -- -- 3.5 -- -- 2.2 VDD - 0.1V -- -- 2.4 -- -- 2.0 -- 2.4 -- Typ* 5.0 10 50 -- -- 10 2.3 -- -- 1.0 -- Max 5.25 15 78.75 -- 1.5 -- 2.5 -- 0.1 10.0 2.7 1.0 0.8 -- 0.4 -- 10.0 Units V mA mW V V M V V V A V k V V V V A -- -- -- -- -- All voltages referenced to VSS unless otherwise noted. VDD = 5.0 V 5%; fC = 3.579545 MHz; A = -40C to +85C, unless otherwise noted. *Typical values are for use as design aids only, and are not guaranteed or subject to production testing. 40-406-00012, Rev. G www.clare.com Page 7 M-8880 Table 12 AC Characteristics PARAMETER Receive signal conditions Valid input signal levels (each tone of composite signal; Notes 1, 2, 3, 5, 6, 9) Positive twist accept (Notes 2, 3, 6, 9) Negative twist accept (Notes 2, 3, 6, 9) Frequency deviation accept (Notes 2, 3, 5, 9) Frequency deviation reject (Notes 2, 3, 5) Third tone tolerance (Notes 2, 3, 4, 5, 9, 10) Noise tolerance (Notes 2, 3, 4, 5, 7, 9, 10) Dial tone tolerance (Notes 2, 3, 4, 5, 8, 9, 11) Call progress Lower frequency (@ -25 dBm) accept Upper frequency (@ -25 dBm) accept Lower frequency (@ -25 dBm) reject Upper frequency (@ -25 dBm) reject Receive timing Tone present detect time Tone absent detect time Tone duration accept (ref. Figure 12) Tone duration reject (ref. Figure 12) Interdigit pause accept (ref. Figure 12) Interdigit pause reject (ref. Figure 12) Delay St to b3 Delay St to RXO--RX3 Transmit timing Tone burst duration (DTMF mode) Tone pause duration (DTMF mode) Tone burst duration (extended, call progress mode) Tone pause duration (extended, call progress mode) Tone output High group output level (RL = 10 k) Low group output level (RL = 10 kW) Pre-emphasis (RL = 10 kW) Output distortion (RL = 10 k, 3.4 kHz bandwidth) Frequency deviation (f = 3.5795 MHz) Output load resistance Microprocessor interface 2 cycle period 2 high pulse width 2 low pulse width 2 rise and fall time Address, R/W hold time Address, R/W setup time (prior to 2) tCYC tCH tCL t R, t F tAH, tRWH tAS, tRWS 0.5 200 180 -- 10 23 -- -- -- -- -- -- 25 -- -- -- -- s ns ns ns ns ns VHOUT VLOUT dBP THD fD RLT -6.1 -8.1 0 -- -- 10 -- -- 2 -25 0.7 -- -2.1 -4.1 3 -- 1.5 50 dBm dBm dB dB % k tBST tPS tBSTE tPSE 50 50 100 100 -- -- -- -- 52 52 104 104 ms ms ms ms tDP tDA tREC tREC tID tDO tPStb3 tPStRX 5 0.5 -- 20 -- 20 -- -- 11 4 -- -- -- -- 13 8 14 8.5 40 -- 40 -- -- -- ms ms ms ms ms ms s s fLA fHA fLR fHR -- -- -- -- 320 510 290 540 -- -- -- -- Hz Hz Hz Hz -29 27.5 -- -- 1.5% 2 Hz 3.5% -- -- -- -- -- -16 -12 +22 -- -- +1 869 6 6 -- -- -- -- -- dBm mVRMS dB dB Nom. Nom. dB dB dB SYMBOL MIN TYP* MAX UNITS 40-406-00012, Rev. G www.clare.com Page 8 M-8880 Table 12 AC Characteristics (continued) Parameter Microprocessor interface (continued) Data hold time (read) f2 to valid data delay (read) (200 pF load) Data setup time (write) Data hold time (write) Input capacitance, D0--D3 Output capacitance, IRQ/CP DTMF clock Crystal clock frequency Clock input rise time (external clock) Clock input fall time (external clock) Clock input duty cycle (external clock) Capacitive load, OSC2 fC tLHCL tHLCL DCCL CLO 3.5759 -- -- 40 -- 3.5795 -- -- 50 -- 3.5831 110 110 60 30 MHz ns ns % pF tDHR tDDR tDSW tDHW CIN C/OUT 22 -- 45 10 -- -- -- -- -- -- 5 5 -- 150 -- -- -- -- ns ns ns ns pF pF Symbol Min Typ* Max Units All voltages referenced to unless otherwise noted. VDD = 5.0 V 5%; VSS = 0 V; fC = 3.579545 MHz; TA = -40C to +85C *Typical values are for use as design aids only, and are not guaranteed or subject to production testing. Notes: 1. dBm = decibels above or below a reference power of 1 mW into a 600 W load. 2. Digit sequence consists of all 16 DTMF tones. 3. Tone duration = 40 ms. Tone pause = 40 ms. 4. Nominal DTMF frequencies are used. 5. Both tones in the composite signal have an equal amplitude. 6. The tone pair is deviated by 1.5% 2 Hz. 7. Bandwidth limited (3 kHz) Gaussian noise. 8. The precise dial tone frequencies are 350 and 440 Hz ( 2%). 9. For an error rate of less than 1 in 10,000. 10. Referenced to the lowest amplitude tone in the DTMF signal. 11. Referenced to the minimum valid accept level. Table 13 Electrical Characteristics - Gain Setting Amplifier Parameter Input leakage current (VSS VIN VDD) Input resistance Input offset voltage Power supply rejection (1 KHz) Common mode rejection (-3.0 V VIN 3.0 V) DC open-loop voltage gain Unity gain bandwidth Output voltage swing (RL 100 K to VSS) Maximum capacitive load, GS Maximum resistive load, GS Common mode range (no load) Symbol IIN RIN VOS PSRR CMRR AVOL BW VO CL RL VCM Min -- -- -- -- -- -- -- -- -- -- -- Typ* 100 10 25 60 60 65 1.5 4.5 100 50 3.0 Max -- -- -- -- -- -- -- -- -- -- -- Units nA M mV dB dB dB MHz VPP pF K VPP All voltages referenced to unless otherwise noted. VDD = 5.0 V; VSS = 0 V; TA = 25C *Typical values are for use as design aids only, and are not guaranteed or subject to production testing. 40-406-00012, Rev. G www.clare.com Page 9 M-8880 Figure 11 Timing Diagrams Figure 12 Test Loads 40-406-00012, Rev. G www.clare.com Page 10 M-8880 Explanation of Events (A) Tone bursts detected, tone duration invalid, RX Data Register not updated. (B) Tone #n detected, tone duration valid, tone decoded and latched in RX Data Register. (C) End of tone #n detected, tone absent duration valid, RX Data Register remain latched until next valid tone. (D) Tone #n + 1 detected, tone duration valid, tone decoded and latched in RX Data Register. (E) Acceptable dropout of tone #n + 1, tone absent duration invalid, RX Data Register remain latched. (F) End of tone #n + 1 detected, tone absent duration valid, RX Data Register remain latched until next valid tone. Explanation of Symbols VIN ESt St/GT RX0-RX3 b3 b2 IRQ/CP tREC tREC tID tDO tDP tDA TGTP tGTA DTMF composite input signal. Early steering output. Indicates detection of valid tone frequencies. Steering input/guard time output. Drives external RC timing circuit. 4-bit decoded data in receive data register. Delayed steering output. Indicates that valid frequencies have been present/absent for the required guard time, thus constituting a valid DTMF signal. Output enable (input). A low level shifts Q1 - Q4 to its high impedance state. Interrupt is active indicating that new data is in the RX data register. The interrupt is cleared after the status register is ready. Maximum DTMF signal duration not detected as valid. Minimum DTMF signal duration required for valid recognition. Minimum time between valid DTMF signals. Maximum allowable dropout during valid DTMF signal. Time to detect the presence of valid DTMF signals. Time to detect the absence of valid DTMF signals. Guard time, tone present. Guard time, tone absent. Figure 13 Timing Diagrams 40-406-00012, Rev. G www.clare.com Page 11 M-8880 A A1 b b2 C D E E1 e ec L Tolerances Inches Metric (mm) Min Max Min Max .210 5.33 .015 .38 .014 .022 .36 .56 .045 .070 1.14 1.78 .008 .014 .20 .36 .980 1.060 24.89 26.92 .300 .325 7.62 8.26 .240 .280 6.10 7.11 .100 BSC 2.54 BSC 15 0 15 0 .115 .150 2.92 3.81 A A1 b D E e H L Tolerances Inches Min Max .093 .104 .004 .012 .013 .020 .496 .512 .291 .299 .050 BSC .394 .419 .016 .050 Metric (mm) Min Max 2.35 2.65 .10 .30 .33 .51 12.60 13.00 7.39 7.59 1.27 BSC 10.00 10.65 .40 1.27 Figure 14 Package Dimensions 40-406-00012, Rev. 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Colombo 10/A I-20066 Melzo (Milano) Tel: 39-02-95737160 Fax: 39-02-95738829 Sweden Clare Sales Comptronic AB Box 167 S-16329 Spanga Tel: 46-862-10370 Fax: 46-862-10371 United Kingdom Clare UK Sales Marco Polo House Cook Way Bindon Road Taunton UK-Somerset TA2 6BG Tel: 44-1-823 352541 Fax: 44-1-823 352797 ASIA PACIFIC Asian Headquarters Clare Room N1016, Chia-Hsin, Bldg II, 10F, No. 96, Sec. 2 Chung Shan North Road Taipei, Taiwan R.O.C. Tel: 886-2-2523-6368 Fax: 886-2-2523-6369 SALES OFFICES AMERICAS Americas Headquarters Clare 78 Cherry Hill Drive Beverly, MA 01915 Tel: 1-978-524-6700 Fax: 1-978-524-4900 Toll Free: 1-800-27-CLARE Eastern Region Clare P.O. Box 856 Mahwah, NJ 07430 Tel: 1-201-236-0101 Fax: 1-201-236-8685 Toll Free: 1-800-27-CLARE Central Region Clare Canada Ltd. 3425 Harvester Road, Suite 202 Burlington, Ontario L7N 3N1 Tel: 1-905-333-9066 Fax: 1-905-333-1824 Northwestern Region Clare 1852 West 11th Street, #348 Tracy, CA 95376 Tel: 1-209-832-4367 Fax: 1-209-832-4732 Toll Free: 1-800-27-CLARE Southwestern Region Clare 2816 Nevis Circle Costa Mesa, CA 92626 Tel: 1-714-556-3661 Fax: 1-714-546-4254 Toll Free: 1-800-27-CLARE Canada Clare Canada Ltd. 3425 Harvester Road, Suite 202 Burlington, Ontario L7N 3N1 Tel: 1-905-333-9066 Fax: 1-905-333-1824 http://www.clare.com Clare cannot assume responsibility for use of any circuitry other then circuitry entirely embodied in this Clare product. No circuit patent licenses nor indemnity are expressed or implied. Clare reserves the right to change the specification and circuitry, without notice at an y time. The products described in this document are not intended for use in medical implantation or other direct life support applications where malfunction may result in direct physical harm, injury or death to a person. Specification: 40-406-00012, Rev. G (c) Copyright 2000, CP Clare Corporation d/b/a Clare All rights reserved. Printed in USA. 07/28/00 |
Price & Availability of M-8880
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